Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This s...
This paper presents an approach to dynamically balance the pipeline by scaling the stage supply voltages. Simulation results show that by such an approach about 50% improvement in...
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
Konrad J. Kulikowski, Ming Su, Alexander B. Smirno...
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...