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SBCCI
2009
ACM
145views VLSI» more  SBCCI 2009»
14 years 3 months ago
Pipelined successive approximation conversion (PSAC) with error correction for a CMOS ophthalmic sensor
The purpose of this work is the proposal of a 10-Bit / 1 MSPS Analog to Digital Converter (ADC) with error correction to match the requirements of a CMOS wavefront sensor for opht...
Frank Sill, Davies W. de Lima Monteiro
IPPS
2006
IEEE
14 years 2 months ago
Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
Among different wireless LAN technologies 802.11a has recently become popular due to its high throughput, large system capacity, and relatively long range. In this paper, we prop...
Maryam Mizani, Daler N. Rakhmatov
APCCAS
2002
IEEE
138views Hardware» more  APCCAS 2002»
14 years 1 months ago
A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter
This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as ...
A. Tamtrakarn, N. Wongkomet
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
14 years 1 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
ISQED
2008
IEEE
118views Hardware» more  ISQED 2008»
14 years 3 months ago
A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors
In multi-core processors there are several ways to pair a thread to a particular core. These load-balancing techniques result in a quite different power, performance and thermal b...
Enric Musoll