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SLIP
2009
ACM
14 years 2 months ago
Floorplan-based FPGA interconnect power estimation in DSP circuits
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic
AIA
2007
13 years 9 months ago
Embedded harmonic control for dynamic trajectory planning on FPGA
This paper presents a parallel hardware implementation of a well-known navigation control method on reconfigurable digital circuits. Trajectories are estimated after an iterated ...
Bernard Girau, Amine M. Boumaza
ISCAS
2007
IEEE
108views Hardware» more  ISCAS 2007»
14 years 1 months ago
A Low Power Digital Baseband for Wireless Endoscope Capsule
— A design of low power digital baseband for wireless endoscope capsule is presented. The key design issues involved in this IC are discussed, including implementation of communi...
Xinkai Chen, Guolin Li, Xiang Xie, XiaoWen Li, Zhi...
ICES
2005
Springer
138views Hardware» more  ICES 2005»
14 years 1 months ago
A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device
Abstract. There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip e...
Kyrre Glette, Jim Torresen
IEICET
2008
106views more  IEICET 2008»
13 years 7 months ago
Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Comm
Finite impulse response (FIR) filtering is the most computationally intensive operation in the channelizer of a wireless communication receiver. Higher order FIR channel filters a...
Jimson Mathew, R. Mahesh, A. Prasad Vinod, Edmund ...