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» Power distribution techniques for dual VDD circuits
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GLVLSI
2006
IEEE
145views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Leakage current starved domino logic
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
Zhiyu Liu, Volkan Kursun
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
14 years 4 months ago
Multigrid-Like Technique for Power Grid Analysis
— Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on ...
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 7 months ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal
GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
13 years 5 months ago
Power distribution paths in 3-D ICS
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
Vasilis F. Pavlidis, Giovanni De Micheli
IPPS
2007
IEEE
14 years 1 months ago
Power-Aware Routing for Well-Nested Communications On The Circuit Switched Tree
Although algorithms that employ dynamic reconfiguration are extremely fast, they need the underlying architecture to change structure very rapidly, possibly at each step of the c...
Hatem M. El-Boghdadi