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» Power distribution techniques for dual VDD circuits
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ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
13 years 6 months ago
A dual-MST approach for clock network synthesis
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangel...
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 8 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
ASPDAC
2008
ACM
122views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Total power optimization combining placement, sizing and multi-Vt through slack distribution management
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
Tao Luo, David Newmark, David Z. Pan
AMEC
2004
Springer
14 years 2 months ago
Agents' Strategies for the Dual Parallel Search in Partnership Formation Applications
In many two-sided search applications, autonomous agents can enjoy the advantage of parallel search, powered by their ability to handle an enormous amount of information, in a shor...
David Sarne, Sarit Kraus
ICCAD
2006
IEEE
103views Hardware» more  ICCAD 2006»
14 years 5 months ago
A statistical framework for post-silicon tuning through body bias clustering
Adaptive body biasing (ABB) is a powerful technique that allows post-silicon tuning of individual manufactured dies such that each die optimally meets the delay and power constrai...
Sarvesh H. Kulkarni, Dennis Sylvester, David Blaau...