732 search results - page 12 / 147 » Power minimization using control generated clocks |
DAC
2003
ACM
14 years 10 months ago
2003
ACM
In this work, we report on an unprecedented design where digital, analog, and MEMS technologies are combined to realize a generalpurpose single-chip CMOS microsystem. The converge...
DATE
2010
IEEE
14 years 2 months ago
2010
IEEE
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...
SECON
2007
IEEE
2007
IEEE
Experimental Investigation of IEEE 802.15.4 Transmission Power Control and Interference Minimization
14 years 3 months ago
Abstract—Although the characteristics of RF transmissions are physically well understood at the lowest levels of communication design, accurately incorporating power and interfer...
ICNP
2009
IEEE
14 years 3 months ago
2009
IEEE
—Clock synchronization is an essential building block for many control mechanisms used in wireless networks, including frequency hopping, power management, and packet scheduling....
CDC
2010
IEEE
13 years 4 months ago
2010
IEEE
This paper is concerned with studying how the minimum power loss in a power system is related to its network topology. The existing algorithms in the literature all exploit nonline...