732 search results - page 4 / 147 » Power minimization using control generated clocks |
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
ASYNC
2005
IEEE
14 years 2 months ago
2005
IEEE
We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Selftimed circuitry both generates and distributes a clock signal, wh...
DAC
2003
ACM
14 years 10 months ago
2003
ACM
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
ISVLSI
2002
IEEE
14 years 1 months ago
2002
IEEE
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is...