390 search results - page 66 / 78 » Power system on a chip (PSoC) |
FPL
2001
Springer
13 years 12 months ago
2001
Springer
System and processor architectures depend on changes in technology. Looking ahead as die density and speed increase, power consumption and on chip interconnection delay become incr...
CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
13 years 11 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
ISLPED
2010
ACM
13 years 7 months ago
2010
ACM
The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depen...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
ISCA
2003
IEEE
14 years 20 days ago
2003
IEEE
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...