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TPDS
1998
122views more  TPDS 1998»
13 years 9 months ago
Managing Statistical Behavior of Large Data Sets in Shared-Nothing Architectures
—Increasingly larger data sets are being stored in networked architectures. Many of the available data structures are not easily amenable to parallel realizations. Hashing scheme...
Isidore Rigoutsos, Alex Delis
IPPS
2010
IEEE
13 years 8 months ago
Speculative execution on multi-GPU systems
Abstract--The lag of parallel programming models and languages behind the advance of heterogeneous many-core processors has left a gap between the computational capability of moder...
Gregory F. Diamos, Sudhakar Yalamanchili
DAC
2004
ACM
14 years 11 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 4 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
14 years 1 months ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...