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MAM
2006
101views more  MAM 2006»
13 years 9 months ago
EPICURE: A partitioning and co-design framework for reconfigurable computing
This paper presents a new design methodology able to bridge the gap between an abstract specification and a heterogeneous recone architecture. The EPICURE contribution is the resu...
Jean-Philippe Diguet, Guy Gogniat, Jean Luc Philip...
CC
2005
Springer
108views System Software» more  CC 2005»
14 years 3 months ago
Task Partitioning for Multi-core Network Processors
Abstract. Network processors (NPs) typically contain multiple concurrent processing cores. State-of-the-art programming techniques for NPs are invariably low-level, requiring progr...
Robert Ennals, Richard Sharp, Alan Mycroft
DAC
1999
ACM
14 years 11 months ago
A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
Jörg Henkel
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
14 years 2 months ago
A hardware environment for prototyping and partitioning based on multiple FPGAs
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
Marc Wendling, Wolfgang Rosenstiel
ICCAD
2009
IEEE
87views Hardware» more  ICCAD 2009»
13 years 7 months ago
Mitigation of intra-array SRAM variability using adaptive voltage architecture
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...
Ashish Kumar Singh, Ku He, Constantine Caramanis, ...