426 search results - page 33 / 86 » Power-Sensitive Multithreaded Architecture |
IWMM
2009
Springer
14 years 3 months ago
2009
Springer
Dynamic binary instrumentation systems are used to inject or modify arbitrary instructions in existing binary applications; several such systems have been developed over the past ...
HPCA
1999
IEEE
14 years 1 months ago
1999
IEEE
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
ICPADS
1998
IEEE
14 years 29 days ago
1998
IEEE
Java-Web Computing paradigm changed Internet into computing environment. For Java-Web Computing and many Java applications, a new Java processor, called simultaneous multithreaded...
HPCA
2005
IEEE
14 years 2 months ago
2005
IEEE
Chip Multi-Threaded (CMT) processors provide support for many simultaneous hardware threads of execution in various ways, including Simultaneous Multithreading (SMT) and Chip Mult...
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...