46 search results - page 8 / 10 » Power-aware issue queue design for speculative instructions |
MICRO
2002
IEEE
14 years 10 days ago
2002
IEEE
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
The negative performance impact of branch mis-predictions can be reduced by exploiting control independence (CI). When a branch mis-predicts, the wrong-path instructions up to the...
SBACPAD
2005
IEEE
14 years 1 months ago
2005
IEEE
Complexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, ...
ARCS
2006
Springer
13 years 11 months ago
2006
Springer
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...