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TVLSI
2002
88views more  TVLSI 2002»
13 years 9 months ago
Least-square estimation of average power in digital CMOS circuits
The estimation of average-power dissipation of a circuit through exhaustive simulation is impractical due to the large number of primary inputs and their combinations. In this brie...
Ashok K. Murugavel, N. Ranganathan, Ramamurti Chan...
GLOBECOM
2007
IEEE
14 years 4 months ago
Network-Calculus-Based Analysis of Power Management in Video Sensor Networks
— This paper considers two important issues for video sensor network, (1) timely delivery of captured video stream and (2) energy-efficient network design. Based on network calc...
Yanchuan Cao, Yuan Xue, Yi Cui
VLSISP
1998
128views more  VLSISP 1998»
13 years 9 months ago
A Low Power DSP Engine for Wireless Communications
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
Ingrid Verbauwhede, Mihran Touriguian
ASPDAC
2009
ACM
104views Hardware» more  ASPDAC 2009»
14 years 4 months ago
Addressing thermal and power delivery bottlenecks in 3D circuits
— The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footpr...
Sachin S. Sapatnekar
PACS
2004
Springer
115views Hardware» more  PACS 2004»
14 years 3 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...