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ISCA
2011
IEEE
270views Hardware» more  ISCA 2011»
12 years 11 months ago
Sampling + DMR: practical and low-overhead permanent fault detection
With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting an...
Shuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Ve...
CODES
2008
IEEE
14 years 2 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
IPSN
2010
Springer
13 years 11 months ago
Practical modeling and prediction of radio coverage of indoor sensor networks
The robust operation of many sensor network applications depends on deploying relays to ensure wireless coverage. Radio mapping aims to predict network coverage based on a small n...
Octav Chipara, Gregory Hackmann, Chenyang Lu, Will...
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
14 years 8 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
DAC
2003
ACM
14 years 8 months ago
A scalable software-based self-test methodology for programmable processors
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit D...