86 search results - page 10 / 18 » Predictable Instruction Caching for Media Processors |
DATE
2000
IEEE
14 years 25 days ago
2000
IEEE
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
RTSS
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
APCSAC
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer ...
HIPC
1999
Springer
14 years 21 days ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
ICS
1999
Tsinghua U.
14 years 20 days ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...