86 search results - page 16 / 18 » Predictable Instruction Caching for Media Processors |
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
The negative performance impact of branch mis-predictions can be reduced by exploiting control independence (CI). When a branch mis-predicts, the wrong-path instructions up to the...
HPCA
2001
IEEE
14 years 7 months ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
ASAP
2007
IEEE
13 years 11 months ago
2007
IEEE
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...
MICRO
2005
IEEE
14 years 28 days ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...