86 search results - page 4 / 18 » Predictable Instruction Caching for Media Processors |
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
RTS
2006
13 years 7 months ago
2006
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
TC
2002
13 years 7 months ago
2002
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction and speculatively executes its data-dependent instructions based on th...
ISCA
2000
IEEE
13 years 11 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...