86 search results - page 8 / 18 » Predictable Instruction Caching for Media Processors |
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
RTAS
1996
IEEE
14 years 17 days ago
1996
IEEE
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
ARCS
2006
Springer
14 years 4 days ago
2006
Springer
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
ISCA
2000
IEEE
14 years 24 days ago
2000
IEEE
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...