Sciweavers

492 search results - page 31 / 99
» Predictable performance in SMT processors
Sort
View
ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
14 years 2 months ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
14 years 1 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
IWMM
2010
Springer
118views Hardware» more  IWMM 2010»
14 years 1 months ago
Speculative parallelization using state separation and multiple value prediction
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
Chen Tian, Min Feng, Rajiv Gupta
ICCD
2006
IEEE
139views Hardware» more  ICCD 2006»
14 years 5 months ago
Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors
Abstract— Recent research has shown that forwarding speculative data to other processors before it is requested can improve the performance of multiprocessor systems. The most re...
Sean Leventhal, Manoj Franklin
ICPP
2006
IEEE
14 years 2 months ago
A Performance Model of the Krak Hydrodynamics Application
We present an analytic performance model of a largescale hydrodynamics code developed at Los Alamos National Laboratory. This modeling work is part of an ongoing effort to develop...
Kevin J. Barker, Scott Pakin, Darren J. Kerbyson