Sciweavers

492 search results - page 38 / 99
» Predictable performance in SMT processors
Sort
View
ISQED
2007
IEEE
128views Hardware» more  ISQED 2007»
14 years 3 months ago
A Model for Timing Errors in Processors with Parameter Variation
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
CF
2010
ACM
14 years 1 months ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...
ICS
2005
Tsinghua U.
14 years 2 months ago
Multigrain parallel Delaunay Mesh generation: challenges and opportunities for multithreaded architectures
Given the importance of parallel mesh generation in large-scale scientific applications and the proliferation of multilevel SMTbased architectures, it is imperative to obtain ins...
Christos D. Antonopoulos, Xiaoning Ding, Andrey N....
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
14 years 3 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
ISSTA
2010
ACM
14 years 22 days ago
Proving memory safety of floating-point computations by combining static and dynamic program analysis
Whitebox fuzzing is a novel form of security testing based on dynamic symbolic execution and constraint solving. Over the last couple of years, whitebox fuzzers have found many ne...
Patrice Godefroid, Johannes Kinder