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» Predictable performance in SMT processors
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DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 3 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
IPPS
2005
IEEE
14 years 2 months ago
Scheduling Processor Voltage and Frequency in Server and Cluster Systems
Modern server farm and cluster sites consume large quantities of energy both to power and cool the machines in the site. At the same time, less power supply redundancy is offered ...
Ramakrishna Kotla, Soraya Ghiasi, Tom W. Keller, F...
APPT
2009
Springer
14 years 3 months ago
A Fast Scheme to Investigate Thermal-Aware Scheduling Policy for Multicore Processors
Abstract. With more cores integrated into one single chip, the overall power consumption from the multiple concurrent running programs increases dramatically in a CMP processor whi...
Liqiang He, Cha Narisu
HICSS
1997
IEEE
120views Biometrics» more  HICSS 1997»
14 years 1 months ago
Building the 4 Processor SB-PRAM Prototype
The SB-PRAM is a massively parallel, uniform memory access (UMA) shared memory computer. The main ideas of the design are multithreading on instruction level, hashing of the addre...
Peter Bach, Michael Braun, Arno Formella, Jör...
APCSAC
2006
IEEE
14 years 2 months ago
A Study of the Performance Potential for Dynamic Instruction Hints Selection
Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer ...
Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu