47 search results - page 4 / 10 » Prefetch-Aware DRAM Controllers |
ISCA
2008
IEEE
14 years 4 months ago
2008
IEEE
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
FCCM
1997
IEEE
14 years 2 months ago
1997
IEEE
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
ASPLOS
2011
ACM
13 years 1 months ago
2011
ACM
Main memory is responsible for a large and increasing fraction of the energy consumed by servers. Prior work has focused on exploiting DRAM low-power states to conserve energy. Ho...
ICCD
2006
IEEE
14 years 6 months ago
2006
IEEE
—The technique of module-threading utilizes standard DDR DRAM components to build modified memory modules. These modified modules incorporate one or more additional control signa...
ISCAS
2008
IEEE
14 years 4 months ago
2008
IEEE
—This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependen...