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ISCAS
2005
IEEE
165views Hardware» more  ISCAS 2005»
14 years 3 months ago
An area-efficient and protected network interface for processing-in-memory systems
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen,...
DIALM
2004
ACM
113views Algorithms» more  DIALM 2004»
14 years 3 months ago
Gathering correlated data in sensor networks
In this paper, we consider energy-efficient gathering of correlated data in sensor networks. We focus on single-input coding strategies in order to aggregate correlated data. For ...
Pascal von Rickenbach, Roger Wattenhofer
DATE
2003
IEEE
93views Hardware» more  DATE 2003»
14 years 3 months ago
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional...
Edwin Rijpkema, Kees G. W. Goossens, Andrei Radule...
DFT
2003
IEEE
132views VLSI» more  DFT 2003»
14 years 3 months ago
Level-Hybrid Optoelectronic TESH Interconnection Network
This paper discusses a hybrid optoelectronic scheme for a new interconnection network, "Tori connected mESHes (TESH)". The major features of TESH are the following: it i...
Vijay K. Jain, Glenn H. Chapman
INFOCOM
2003
IEEE
14 years 3 months ago
On-line Tuning of Prices for Network Services
— Recent investigations into the pricing of multiclass loss networks have shown that static prices are optimal in the asymptotic regime of many small sources. These results sugge...
Enrique Campos-Náñez, Stephen D. Pat...