In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fau...
The SPIN model checker and its specification language Promela have been used extensively in industry and academia to check logical properties of distributed algorithms and protoc...
Abstract-- When dealing with massive quantities of data, topk queries are a powerful technique for returning only the k most relevant tuples for inspection, based on a scoring func...
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...