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DATE
2004
IEEE
129views Hardware» more  DATE 2004»
13 years 11 months ago
On the Design and Verification Methodology of the Look-Aside Interface
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Moha...
ITC
1997
IEEE
119views Hardware» more  ITC 1997»
13 years 11 months ago
Testability Analysis and ATPG on Behavioral RT-Level VHDL
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fau...
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
SCP
2010
155views more  SCP 2010»
13 years 5 months ago
Type inference and strong static type checking for Promela
The SPIN model checker and its specification language Promela have been used extensively in industry and academia to check logical properties of distributed algorithms and protoc...
Alastair F. Donaldson, Simon J. Gay
ICDE
2009
IEEE
170views Database» more  ICDE 2009»
14 years 9 months ago
Semantics of Ranking Queries for Probabilistic Data and Expected Ranks
Abstract-- When dealing with massive quantities of data, topk queries are a powerful technique for returning only the k most relevant tuples for inspection, based on a scoring func...
Graham Cormode, Feifei Li, Ke Yi
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
13 years 11 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt