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DAC
2009
ACM
14 years 11 months ago
Spare-cell-aware multilevel analytical placement
Post-silicon validation has recently drawn designers' attention due to its increasing impacts on the VLSI design cycle and cost. One key feature of the post-silicon validatio...
Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yu...
DAC
2008
ACM
14 years 11 months ago
Stochastic integral equation solver for efficient variation-aware interconnect extraction
In this paper we present an efficient algorithm for extracting the complete statistical distribution of the input impedance of interconnect structures in the presence of a large n...
Tarek Moselhy, Luca Daniel
DAC
2007
ACM
14 years 11 months ago
Optimization of Area in Digital FIR Filters using Gate-Level Metrics
In the paper, we propose a new metric for the minimization of area in the generic problem of multiple constant multiplications, and demonstrate its effectiveness for digital FIR f...
Eduardo A. C. da Costa, José C. Monteiro, L...
DAC
2004
ACM
14 years 11 months ago
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs
The negative effect of electromigration on signal and power line lifetime and functional reliability is an increasingly important problem for the physical design of integrated cir...
Goeran Jerke, Jürgen Scheible, Jens Lienig
DAC
2004
ACM
14 years 11 months ago
Reducing clock skew variability via cross links
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approac...
Anand Rajaram, Jiang Hu, Rabi N. Mahapatra