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» Process Isolation for Reconfigurable Hardware
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CODES
2003
IEEE
14 years 28 days ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
FPGA
2000
ACM
141views FPGA» more  FPGA 2000»
13 years 11 months ago
Tolerating operational faults in cluster-based FPGAs
In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain ...
Vijay Lakamraju, Russell Tessier
SBACPAD
2007
IEEE
110views Hardware» more  SBACPAD 2007»
14 years 1 months ago
Architectural Breakdown of End-to-End Latency in a TCP/IP Network
Adoption of the 10GbE Ethernet standard has been impeded by two important performance-oriented considerations: 1) processing requirements of common protocol stacks and 2) end-to-e...
Steen Larsen, Parthasarathy Sarangam, Ram Huggahal...
SIGMETRICS
2012
ACM
290views Hardware» more  SIGMETRICS 2012»
11 years 10 months ago
Power and energy containers for multicore servers
Energy efficiency and power capping remain growing concerns in server systems. Online applications continue to evolve with new features and dynamic clientdirected processing, res...
Kai Shen, Arrvindh Shriraman, Sandhya Dwarkadas, X...
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang