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DAC
2004
ACM
14 years 9 months ago
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory
Massive data transfer encountered in emerging multimedia embedded applications requires architecture allowing both highly distributed memory structure and multiprocessor computati...
Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik...
ISCA
2011
IEEE
290views Hardware» more  ISCA 2011»
13 years 13 days ago
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as thos...
Blas Cuesta, Alberto Ros, María Engracia G&...
ISPASS
2007
IEEE
14 years 3 months ago
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads
Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication beha...
Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark Heinric...
ECRTS
2006
IEEE
14 years 2 months ago
Task Reweighting under Global Scheduling on Multiprocessors
We consider schemes for enacting task share changes—a process called reweighting—on real-time multiprocessor platforms. Our particular focus is reweighting schemes that are de...
Aaron Block, James H. Anderson, UmaMaheswari C. De...
SIGARCH
2008
94views more  SIGARCH 2008»
13 years 8 months ago
Parallelization, performance analysis, and algorithm consideration of Hough transform on chip multiprocessors
This paper presents a parallelization framework for emerging applications on the future chip multiprocessors (CMPs). With the continuing prevalence of CMP and the number of on-die...
Wenlong Li, Yen-Kuang Chen