Sciweavers

659 search results - page 70 / 132
» Process Modeling in the telco industry
Sort
View
UML
2004
Springer
14 years 2 months ago
The AGEDIS Tools for Model Based Testing
We describe the tools and interfaces created by the AGEDIS project, a European Commission sponsored project for the creation of a methodology and tools for automated model driven ...
Alan Hartman, Kenneth Nagin
DAC
2003
ACM
14 years 10 months ago
Learning from BDDs in SAT-based bounded model checking
Bounded Model Checking (BMC) based on Boolean Satisfiability (SAT) procedures has recently gained popularity as an alternative to BDD-based model checking techniques for finding b...
Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Ya...
ISSRE
2007
IEEE
13 years 11 months ago
Data Mining Techniques for Building Fault-proneness Models in Telecom Java Software
This paper describes a study performed in an industrial setting that attempts to build predictive models to identify parts of a Java system with a high probability of fault. The s...
Erik Arisholm, Lionel C. Briand, Magnus Fuglerud
ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
14 years 6 months ago
A succinct memory model for automated design debugging
— In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to t...
Brian Keng, Hratch Mangassarian, Andreas G. Veneri...
GLVLSI
2009
IEEE
150views VLSI» more  GLVLSI 2009»
14 years 4 months ago
Contradictory antecedent debugging in bounded model checking
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
Daniel Große, Robert Wille, Ulrich Kühn...