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DEBS
2010
ACM
13 years 11 months ago
Workload characterization for operator-based distributed stream processing applications
Operator-based programming languages provide an effective development model for large scale stream processing applications. A stream processing application consists of many runtim...
Xiaolan J. Zhang, Sujay Parekh, Bugra Gedik, Henri...
CODES
2003
IEEE
14 years 1 months ago
RTOS scheduling in transaction level models
the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impa...
Haobo Yu, Andreas Gerstlauer, Daniel Gajski
CODES
2007
IEEE
14 years 3 months ago
HW/SW co-design for Esterel processing
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...
Sascha Gädtke, Claus Traulsen, Reinhard von H...
JCM
2007
76views more  JCM 2007»
13 years 8 months ago
Scheduling Small Packets in IPSec Multi-accelerator Based Systems
—IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these ...
Antonio Vincenzo Taddeo, Alberto Ferrante, Vincenz...
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 8 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek