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ISPAN
2005
IEEE
14 years 1 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
14 years 1 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
CODES
2003
IEEE
14 years 23 days ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
SIGMETRICS
1993
ACM
106views Hardware» more  SIGMETRICS 1993»
13 years 11 months ago
Software Performance Engineering
: Performance is critical to the success of today’s software systems. However, many software products fail to meet their performance objectives when they are initially constructe...
Connie U. Smith
JVCIR
2008
92views more  JVCIR 2008»
13 years 7 months ago
Hardware implementation of a disparity estimation scheme for real-time compression in 3D imaging applications
This paper presents a novel hardware implementation of a disparity estimation scheme targeted to real-time Integral Photography (IP) image and video sequence compression. The soft...
Dionisis Chaikalis, Nikos Sgouros, Dimitris Maroul...