154 search results - page 9 / 31 » Process Scheduling for Performance Estimation and Synthesis ... |
131
Voted
ICCAD
1991
IEEE
15 years 7 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
144
Voted
IEEEPACT
2006
IEEE
15 years 9 months ago
2006
IEEE
This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...
118
Voted
ISLPED
1999
ACM
15 years 7 months ago
1999
ACM
Abstract – In this paper, we propose a modeling approach for the average power consumption of macro-blocks that are typically used in digital signal processing (DSP) systems, suc...
145
Voted
PDP
2010
IEEE
15 years 7 months ago
2010
IEEE
The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
128
Voted
ICCAD
2004
IEEE
16 years 13 days ago
2004
IEEE
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...