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» Process Variations and their Impact on Circuit Operation
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ISQED
2008
IEEE
103views Hardware» more  ISQED 2008»
14 years 1 months ago
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation
Negative bias temperature instability (NBTI) is one of the primary limiters of reliability lifetime in nano-scale integrated circuits. NBTI manifests itself in a gradual increase ...
Bin Zhang, Michael Orshansky
VLSID
2005
IEEE
116views VLSI» more  VLSID 2005»
14 years 7 months ago
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
C. Brej, Jim D. Garside
TVLSI
2008
176views more  TVLSI 2008»
13 years 7 months ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
DATE
2010
IEEE
178views Hardware» more  DATE 2010»
14 years 13 days ago
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...
ISQED
2009
IEEE
111views Hardware» more  ISQED 2009»
14 years 2 months ago
Efficient statistical analysis of read timing failures in SRAM circuits
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pilegg...