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» Process Variations and their Impact on Circuit Operation
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TVLSI
2008
153views more  TVLSI 2008»
13 years 7 months ago
Characterization of a Novel Nine-Transistor SRAM Cell
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
Zhiyu Liu, Volkan Kursun
DAC
2006
ACM
14 years 1 months ago
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the deg...
Rakesh Vattikonda, Wenping Wang, Yu Cao
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
14 years 1 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
DFT
2004
IEEE
118views VLSI» more  DFT 2004»
13 years 11 months ago
Defect Characterization for Scaling of QCA Devices
Quantum dot Cellular Automata (QCA) is amongst promising new computing scheme in the nano-scale regimes. As an emerging technology, QCA relies on radically different operations in...
Jing Huang, Mariam Momenzadeh, Mehdi Baradaran Tah...
NOCS
2008
IEEE
14 years 1 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...