137 search results - page 10 / 28 » Process variation dimension reduction based on SVD |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
IUI
2010
ACM
13 years 10 months ago
2010
ACM
We present Luminoso, a tool that helps researchers to visualize and understand a dimensionality-reduced semantic space by exploring it interactively. It also streamlines the proce...
AIPR
2003
IEEE
14 years 1 months ago
2003
IEEE
Although hyperspectral images provide abundant information about objects, their high dimensionality also substantially increases computational burden. Dimensionality reduction off...
WCNC
2008
IEEE
14 years 2 months ago
2008
IEEE
A primary constraint in wireless sensor networks (WSNs) is obtaining reliable and prolonged network operation with power-limited sensor nodes. Most of the approaches to the energy ...