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ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
13 years 11 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
CMSB
2009
Springer
14 years 2 months ago
Modelling Biological Clocks with Bio-PEPA: Stochasticity and Robustness for the Neurospora crassa Circadian Network
Circadian clocks are biochemical networks, present in nearly all living organisms, whose function is to regulate the expression of specific mRNAs and proteins to synchronise rhyth...
Ozgur E. Akman, Federica Ciocchetta, Andrea Degasp...
ICCAD
1993
IEEE
123views Hardware» more  ICCAD 1993»
13 years 11 months ago
Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models
We have proposed an e cient measure to reduce the clock skew by assigning the clock network with variable branch widths. This measure has long been used for \H" clock tree. T...
Qing Zhu, Wayne Wei-Ming Dai, Joe G. Xi
ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
13 years 5 months ago
A dual-MST approach for clock network synthesis
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangel...
DAC
2010
ACM
13 years 5 months ago
Non-uniform clock mesh optimization with linear programming buffer insertion
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis