40 search results - page 5 / 8 » Process variation tolerant low power DCT architecture |
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
ICCD
2008
IEEE
14 years 1 months ago
2008
IEEE
— SRAMs typically represent half of the area and more than half of the transistors on a chip today. Variability increases as feature size decreases, and the impact of variability...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the hi...
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
: The accumulation of popular features in portable products such as mobile handsets is driving battery life to unacceptably low levels. Substantial change will not come from increm...
CASES
2009
ACM
13 years 10 months ago
2009
ACM
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...