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» Processor Architectures for Ontogenesis
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ANSS
2000
IEEE
15 years 9 months ago
Using the DEVS Paradigm to Implement a Simulated Processor
This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of th...
Sergio Daicz, Alejandro Troccoli, Sergio Zlotnik, ...
ISCA
1998
IEEE
134views Hardware» more  ISCA 1998»
15 years 8 months ago
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, par...
Stephen W. Keckler, William J. Dally, Daniel Maski...
ASAP
1995
IEEE
145views Hardware» more  ASAP 1995»
15 years 8 months ago
An array processor for inner product computations using a Fermat number ALU
This paper explores an architecture for parallel independent computations of inner products over the direct product ring . The structure is based on the polynomial mapping of the ...
Wenzhe Luo, Graham A. Jullien, Neil M. Wigley, Wil...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
16 years 1 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
MICRO
2008
IEEE
113views Hardware» more  MICRO 2008»
15 years 11 months ago
From SODA to scotch: The evolution of a wireless baseband processor
With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly chan...
Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, ...