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» Processor Architectures for Ontogenesis
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LSSC
2005
Springer
15 years 10 months ago
Systolic Architecture for Adaptive Censoring CFAR PI Detector
A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adap...
Ivan Garvanov, Christo A. Kabakchiev, Plamen Daska...
DAC
1996
ACM
15 years 8 months ago
Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures
The advent of parallel executing Address Calculation Units (ACUs) in Digital Signal Processor (DSP) and Application Specific InstructionSet Processor (ASIP) architectures has made...
Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerra...
IPPS
2007
IEEE
15 years 10 months ago
Experimental Evaluation of Emerging Multi-core Architectures
The trend of increasing speed and complexity in the single-core processor as stated in the Moore’s law is facing practical challenges. As a result, the multi-core processor arch...
Abdullah Kayi, Yiyi Yao, Tarek A. El-Ghazawi, Greg...
ISCA
1997
IEEE
96views Hardware» more  ISCA 1997»
15 years 8 months ago
DataScalar Architectures
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
Doug Burger, Stefanos Kaxiras, James R. Goodman
HPCA
2001
IEEE
16 years 4 months ago
An Architectural Evaluation of Java TPC-W
The use of the Java programming language for implementing server-side application logic is increasing in popularity, yet there is very little known about the architectural require...
Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko ...