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CSSE
2008
IEEE
15 years 11 months ago
Generation of Executable Representation for Processor Simulation with Dynamic Translation
Instruction-Set Simulators (ISS) are indispensable tools for studying new architectures. There are several alternatives to achieve instruction set simulation, such as interpretive...
Jiajia Song, HongWei Hao, Claude Helmstetter, Vani...
ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
15 years 10 months ago
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
M. D. Linderman, T. H. Meng
DATE
2010
IEEE
184views Hardware» more  DATE 2010»
15 years 9 months ago
Parallel subdivision surface rendering and animation on the Cell BE processor
—Subdivision Surfaces provide a compact way to describe a smooth surface using a mesh model. They are widely used in 3D animation and nearly all modern modeling programs support ...
R. Grottesi, S. Morigi, Martino Ruggiero, Luca Ben...
116
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COMPCON
1996
IEEE
15 years 8 months ago
Broadband Algorithms with the MicroUnity MediaProcessor
An important objective of the MicroUnity mediaprocessor is to allow the design of systems that replace hardwired functionality with software. One of the key design techniques that...
Curtis Abbott, Henry Massalin, Kevin Peterson, Tom...
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
15 years 8 months ago
Analysis and optimization of fault-tolerant embedded systems with hardened processors
1 In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques...
Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru ...