Sciweavers

2700 search results - page 135 / 540
» Processor Architectures for Ontogenesis
Sort
View
WAE
2001
281views Algorithms» more  WAE 2001»
15 years 6 months ago
Using PRAM Algorithms on a Uniform-Memory-Access Shared-Memory Architecture
The ability to provide uniform shared-memory access to a significant number of processors in a single SMP node brings us much closer to the ideal PRAM parallel computer. In this pa...
David A. Bader, Ajith K. Illendula, Bernard M. E. ...
DAC
2002
ACM
16 years 5 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...
VLSID
1993
IEEE
133views VLSI» more  VLSID 1993»
15 years 8 months ago
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters
An area-eficzent systolic architecture for realtime, programmable-coeBcient jinite impulse response (FIR)filters is presented. A technique called pipelined clustering is introduce...
V. Visvanathan, Nibedita Mohanty, S. Ramanathan
MTV
2003
IEEE
109views Hardware» more  MTV 2003»
15 years 9 months ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt
ICDE
2009
IEEE
114views Database» more  ICDE 2009»
16 years 6 months ago
On Efficient Query Processing of Stream Counts on the Cell Processor
In recent years, the sketch-based technique has been presented as an effective method for counting stream items on processors with limited storage and processing capabilities, such...
Dina Thomas, Rajesh Bordawekar, Charu C. Aggarwal,...