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» Processor Architectures for Ontogenesis
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134
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WMPI
2004
ACM
15 years 10 months ago
A low cost, multithreaded processing-in-memory system
This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of ...
Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. ...
RTCSA
2000
IEEE
15 years 9 months ago
Fixed-priority preemptive multiprocessor scheduling: to partition or not to partition
Traditional multiprocessor real-time scheduling partitions a task set and applies uniprocessor scheduling on each processor. By allowing a task to resume on another processor than...
Björn Andersson, Jan Jonsson
DAC
1996
ACM
15 years 8 months ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
131
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ICCD
1992
IEEE
124views Hardware» more  ICCD 1992»
15 years 8 months ago
The ETCA Data-Flow Functional Computer for Real-Time Image Processing
This paper presents a data- ow computer, constituted of a large array of data- ow processors and programmed using a functional language, and its application to realtime image proc...
Georges Quénot, Bertrand Zavidovique
FCCM
2004
IEEE
269views VLSI» more  FCCM 2004»
15 years 8 months ago
FPGA Based Network Intrusion Detection using Content Addressable Memories
In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). Current software-based NIDS are too compute intensive and can not ...
Long Bu, John A. Chandy