378 search results - page 45 / 76 » Processor Modeling for Hardware Software Codesign |
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
Compositional approaches to system-level performance analysis have shown great flexibility and scalability in the design of heterogeneous systems. These approaches often assume c...
CODES
2003
IEEE
14 years 21 days ago
2003
IEEE
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
TVLSI
2008
2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
13 years 7 months ago
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...