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» Processor Modeling for Hardware Software Codesign
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CODES
2001
IEEE
14 years 5 days ago
Towards effective embedded processors in codesigns: customizable partitioned caches
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
Peter Petrov, Alex Orailoglu
ICRA
2010
IEEE
189views Robotics» more  ICRA 2010»
13 years 7 months ago
Affordable SLAM through the co-design of hardware and methodology
— Simultaneous localization and mapping (SLAM) is a prominent feature for autonomous robots operating in undefined environments. Applications areas such as consumer robotics app...
Stéphane Magnenat, Valentin Longchamp, Mich...
CODES
2003
IEEE
14 years 1 months ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
CODES
1999
IEEE
14 years 25 days ago
How standards will enable hardware/software co-design
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
Mark Genoe, Christopher K. Lennard, Joachim Kunkel...
CODES
2006
IEEE
14 years 2 months ago
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffe...
Roshan G. Ragel, Sri Parameswaran