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ASPLOS
2010
ACM
13 years 11 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
ANCS
2008
ACM
13 years 9 months ago
A programmable architecture for scalable and real-time network traffic measurements
Accurate and real-time traffic measurement is becoming increasingly critical for large variety of applications including accounting, bandwidth provisioning and security analysis. ...
Faisal Khan, Lihua Yuan, Chen-Nee Chuah, Soheil Gh...
ASPLOS
2008
ACM
13 years 9 months ago
The mapping collector: virtual memory support for generational, parallel, and concurrent compaction
Parallel and concurrent garbage collectors are increasingly employed by managed runtime environments (MREs) to maintain scalability, as multi-core architectures and multi-threaded...
Michal Wegiel, Chandra Krintz
CASES
2008
ACM
13 years 9 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...
ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
13 years 9 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
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