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CF
2005
ACM
13 years 11 months ago
Exploiting processor groups to extend scalability of the GA shared memory programming model
Exploiting processor groups is becoming increasingly important for programming next-generation high-end systems composed of tens or hundreds of thousands of processors. This paper...
Jarek Nieplocha, Manojkumar Krishnan, Bruce Palmer...
VLSISP
2008
123views more  VLSISP 2008»
13 years 9 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
ICCAD
2005
IEEE
141views Hardware» more  ICCAD 2005»
14 years 6 months ago
Architecture and compilation for data bandwidth improvement in configurable embedded processors
Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in t...
Jason Cong, Guoling Han, Zhiru Zhang
IPPS
2009
IEEE
14 years 3 months ago
Optimizing assignment of threads to SPEs on the cell BE processor
The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by ...
C. Devi Sudheer, T. Nagaraju, Pallav K. Baruah, As...
ARCS
2010
Springer
14 years 3 months ago
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-ti...
Jörg Mische, Irakli Guliashvili, Sascha Uhrig...