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ISCA
1998
IEEE
134views Hardware» more  ISCA 1998»
14 years 1 months ago
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, par...
Stephen W. Keckler, William J. Dally, Daniel Maski...
MICRO
2000
IEEE
88views Hardware» more  MICRO 2000»
13 years 9 months ago
Two-level hierarchical register file organization for VLIW processors
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
Javier Zalamea, Josep Llosa, Eduard Ayguadé...
HOTNETS
2010
13 years 4 months ago
Diagnosing mobile applications in the wild
There are a lot of applications that run on modern mobile operating systems. Inevitably, some of these applications fail in the hands of users. Diagnosing a failure to identify the...
Sharad Agarwal, Ratul Mahajan, Alice Zheng, Victor...
ICIP
2004
IEEE
14 years 11 months ago
A smart camera for face recognition
There is a rapidly growing demand for using smart cameras for various biometric applications in surveillance. Although having a small form-factor, most of these applications deman...
Ben J. A. Kröse, Harry Broers, Martijn Reuver...
CASES
2005
ACM
13 years 11 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...