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ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
14 years 21 days ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
CLUSTER
2008
IEEE
14 years 3 months ago
Context-aware address translation for high performance SMP cluster system
—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface...
Moon-Sang Lee, Joonwon Lee, Seungryoul Maeng
SP
2008
IEEE
122views Security Privacy» more  SP 2008»
13 years 8 months ago
Large-scale phylogenetic analysis on current HPC architectures
Abstract. Phylogenetic inference is considered a grand challenge in Bioinformatics due to its immense computational requirements. The increasing popularity and availability of larg...
Michael Ott, Jaroslaw Zola, Srinivas Aluru, Andrew...
IPPS
2006
IEEE
14 years 2 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
HPDC
2005
IEEE
14 years 2 months ago
Dynamic load balancing for distributed search
This paper examines how computation can be mapped across the nodes of a distributed search system to effectively utilize available resources. We specifically address computationa...
Larry Huston, Alex Nizhner, Padmanabhan Pillai, Ra...