LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation

The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last level cache. However, larger caches threaten to dramatically increase the leakage power as the industry moves into deeper sub-micron technology. In this paper, with the aim of reducing leakage energy we introduce LEMap (Low Energy Map), a novel virtual address translation scheme to control the set of physical pages mapped to each bank of a large multi-banked non-uniform access L2 cache shared across all the cores. Combination of profiling, a simple off-line clustering algorithm, and a new flavor of Irix-style application-directed page placement system call maps the virtual pages that are accessed in the L2 cache roughly together onto the same region of the cache. Thus LEMap makes the access windows of the pages mapped to a region roughly identical and increases the average idle time of a region. As a result,...

• Type: Conference
• Year: 2007
• Where: ICCD
• Authors: Jugash Chandarlapati, Mainak Chaudhuri
• Keywords: Access L2 Cache, Cache Energy, Hardware, ICCD 2007, L2 Cache