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FPL
2003
Springer
136views Hardware» more  FPL 2003»
14 years 1 months ago
FPGAs for High Accuracy Clock Synchronization over Ethernet Networks
This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The netw...
Roland Höller
HIPEAC
2007
Springer
14 years 2 months ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...
IJCNN
2006
IEEE
14 years 2 months ago
A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering
— We describe an implementation of Gabor-type filters on field programmable gate arrays using the cellular neural network (CNN) architecture. The CNN template depends upon the ...
Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K....
CODES
2005
IEEE
14 years 1 months ago
FlexPath NP: a network processor concept with application-driven flexible processing paths
In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP...
Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild
ICC
2000
IEEE
129views Communications» more  ICC 2000»
14 years 15 days ago
Control and Coordination of Interactive Videoconferencing over Hybrid Networks
−−−−This paper describes the field trial experience on the control and coordination of an interactive videoconferencing system. The system employs ATM and Internet networks...
Ting-Chao Hou, Chorng-Horng Yang, Yuan-Sun Chu, Ki...