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FPL
2008
Springer
107views Hardware» more  FPL 2008»
13 years 9 months ago
Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. However, this approach results in inefficient memory utilization. Due to available...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
DATE
2007
IEEE
105views Hardware» more  DATE 2007»
14 years 1 months ago
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
We propose in this paper an algorithm for off-line selection of the contents of on-chip memories. The algorithm supports two types of on-chip memories, namely locked caches and sc...
Isabelle Puaut, Christophe Pais
IPPS
2000
IEEE
13 years 12 months ago
Support for Recoverable Memory in the Distributed Virtual Communication Machine
The Distributed Virtual Communication Machine (DVCM) is a software communication architecture for clusters of workstations equipped with programmable network interfaces (NIs) for ...
Marcel-Catalin Rosu, Karsten Schwan
ENTCS
2010
125views more  ENTCS 2010»
13 years 4 months ago
Concrete Memory Models for Shape Analysis
This paper discusses four store-based concrete memory models. We characterize memory models by the class of pointers they support and whether they use numerical or symbolic offset...
Pascal Sotin, Bertrand Jeannet, Xavier Rival
FPL
2003
Springer
100views Hardware» more  FPL 2003»
14 years 20 days ago
An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. The firewall use...
John W. Lockwood, Christopher E. Neely, Christophe...